Boolean Decomposition in Combinational Logic Synthesis
نویسنده
چکیده
Today’s digital designs have reached a magnitude making it intractable for humans to develop designs on a gate level. Large designs are developed with help of hardware description languages like VHDL, or with other methods using high level of abstraction. Computer based synthesis tools are applied to transfer those descriptions to layouts for implementation in programmable circuits like Field Programmable Gate Array (FPGAs) or for implementation in full custom integrated circuits. In order to obtain a good implementation, it is important to perform optimization of the design during the transformation from high level description to layout. This thesis is in the area of Boolean decomposition. Decomposition is a technique used to increase the number of levels in a Boolean formula. Decomposition aims at representing a logic function by a multi-level expression with the least number of literals. A multi-level expression is usually simpler than a sum-of-product expression representing the same function. In many design styles, the implementation of a function is related to its multi-level expression. For instance, in complex gate CMOS, the number of transistors in the circuit is roughly proportional to the number of literals in its multi-level expression and therefore can be used as a measure of circuit area. One contribution of this thesis is a heuristic algorithm for disjoint decomposition of a Boolean function based on its representation as a Reduced Ordered Binary Decision Diagram (ROBDD). Two distinct features make the algorithm feasible for large functions. First, for an n-variable function, it checks only O(n) candidates for decomposition out of O(2) possible ones. A special strategy for selecting candidates makes it likely that all other decompositions are encoded in the selected ones. Second, the decompositions for the approved candidates are computed using a novel IntervalCut algorithm. This algorithm does not require re-ordering of the ROBDD. The experimental results on 582 benchmark functions show that the presented heuristic finds 95% of all decompositions on average. For 526 of those functions, it finds 100% of the decompositions. Another contribution of this thesis is in the area of XOR-based synthesis. In many cases, functions with embedded XOR logic have very large expressions in terms of AND, OR and NOT operations. Vice versa, functions which do not have embedded XOR logic might have larger representation if expressed using AND, XOR and NOT. Since both, AND-OR and AND-XOR, minimization algorithms are quite time-consuming for large functions, it is attractive to know a priori which of them should be used for a given function. In this thesis a solution to this problem is given. We formulate a sufficient condition for Boolean functions to have a decomposition of type f = (g⊕h)+ r, with the total number of product-terms in g, h and r smaller than the number of product-terms in f . This condition is used to develop an algorithm for deciding whether a given function is likely to benefit from XOR minimization.
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